As VLSI technology continues to scale, the number of wires in an integrated circuit, as well as the impact of the wires on circuit delay, noise, and power dissipation, increases rapidly. Hence, impedance extraction techniques that are computationally efficient as well as reasonably accurate are desired. However, interconnect impedance extraction presents a challenging task owing to the sheer size of the problem, both in terms of computation time and required memory. The complexity of the extraction problem is further compounded as lithography scaling enables faster transistors, driving maximum signal propagation frequencies on interconnects into the range of 20-100 GHz. In this frequency regime, it is desirable to analyze the effect on interconnect circuit parameters arising from the presence of complex substrate structures underneath or over the interconnect layers. The underlying physics includes, for example, transient currents in interconnects that are the sources of time-varying magnetic fields, which in turn induce currents in other interconnects as well as eddy currents in the lossy substrate. The presence of these eddy currents modifies the impedance matrix of the interconnects. At high frequencies, the effect of a low resistivity substrate on interconnect impedance can be a matter of significant concern. Often, a very high-resistivity (˜1000 Ω−cm) substrate is used (underlying a low-resistivity surface layer for active devices) in radio-frequency or mixed-signal ICs in order to substantially decrease the importance of substrate eddy currents. However, low-resistivity substrates continue to be used for latch-up avoidance. Hence, in order to efficiently and accurately compute the impact of the multi-layer substrate on interconnect impedance, it is desirable to use a parasitic extraction methodology that incorporates this effect.
In general, conventional interconnect extraction tools are too expensive, in terms of computation time and/or memory, to handle this problem. For example, with the industry standard tool FastHenry, the substrate must be specified as an explicit conductive layer(s) demanding several thousand filaments at high frequencies. The resulting linear system is rapidly overwhelmed by the size requirements related to the partitioning of the substrate, even for single-layer substrate media. This constitutes orders of magnitude overhead in computation time and memory requirements, even for the simplest interconnect configurations.
Accordingly, improved methods for performing interconnect impedance extraction in the presence of a multi-layer conductive substrate are desired.